1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
In a conventional dynamic read and write memory (hereinafter referred to as a DRAM), bit lines are connected to each source of a plurality of N-channel MOS transistors (hereinafter referred to as a NMOS) including a plurality of memory cells. The gates of the NMOS transistors are connected to word lines for selecting a memory cell to be accessed. The drains of the NMOS tranisitors are grounded through capacitors. The two bit lines are connected to each other through the sense amplifier.
When a stored data is read out in such a DRAM, supplying of a high (H) level signal to the selected word line turns the NMOS transistor ON, thereby the capacitor and the bit line become conductive. Because the bit line has a parasitic capacitor, the electric potential of the bit line becomes a balanced electric potential of the charge stored in the capacitor and the charge in the parasitic capacitor. Therefore, a potential difference develops between the bit line and another bit line connected to another memory cell where the word line is not selected. The developed potential difference is amplified by the sense amplifier. This potential difference between the bit line and the other bit line 0.2 volts at most.
A trend in recent years is that the capacitors in the memory cells are getting smaller, while on the contrary the capacitance of the parasitic capacitors of the bit lines is getting larger due to high density DRAMS. For this reason, the above described potential difference tends to decrease. The sense amplifier can be operated by a variation of a potential difference caused by noise. Thus, such a small potential difference hinders stable operation of the sense amplifier and is responsible for a problem in which the operation speed of the sense amplifier is limited because it takes time to ampifly the small potential difference.